The present invention relates to floating point number data processing means for use with microprocessor systems and in particular to a low precision floating point number format.
The present invention finds application in AC motor drive technology where, for example, a small motor may draw half an amp of current and a large motor may draw 200 amps of current, and the frequency range of such motors is very large.
Many known floating point systems are realised in pure software. This is a slow process, typically taking tens or hundreds of micro-seconds per operation.
Existing microcontrollers use integer arithmetic. In many control applications, the range of variables results in a scaling calculation at every calculation step in order to maintain accuracy while avoiding overflow. Floating point variables and arithmetic solve this problem.
Floating point mathematics hardware is available to the universally accepted IEEE format. The standard precision for this format requires 4 or 5 bytes storage as mentioned above. The range and accuracy of these numbers far exceeds most control requirements. The hardware to implement mathematic functions is complex and operates slowly. Several memory operations are required to load each operand into the floating point unit and the result out.
A floating point comparison, e.g. the control statement if (A less than B) then, requires a full floating point subtraction and inspection of the sign of the result. This very common control function becomes rather time consuming.
An aim of the present invention is to provide means for performing operations on a floating point number format which does not suffer from the above disadvantages experienced in the prior art.
According to the present invention there is provided means for performing operations with respect to a floating point number format, comprising n bits of data, where n is substantially smaller than known formats, wherein said means is a data processing means which operates upon said format combinatorially.
The format comprises a sign bit, a 7 bit signed exponent, and an 8 bit mantissa.
The format is designed such that an unsigned integer comparison of floating point numbers yields the correct result.
The data processor may be a microprocessor system having an associated gate array.